In the field of large computer installations, one or several central processor units (known as CPUs) are often connectable to peripheral devices through a switch matrix. Channels of the CPUs are connected to channel ports of the switch matrix and peripheral devices such as card readers, printers, tape and disk drives are connected to peripheral ports of the switch matrix. Crosspoints in the matrix are then controlled so that a CPU can be connected to one or more peripheral ports and peripheral devices.
Control over the matrix establishes a configuration that is hopefully an efficient one in which the CPUs are kept about equally busy. The switch matrix enables one to alter the configuration in a rapid manner so as to minimize down time in case of an equipment failure. For example, if a critically important CPU fails, this can be quickly disconnected and another one inserted. The complexity of such a switch matrix can be appreciated when one considers that each CPU may have a large number of input/output channels, such as 16, with each channel often formed of over sixty coaxial conductors, and with a channel connected to many peripheral devices, frequently as many as twenty four. Matrix switches may be as large as 16.times.24, i.e. 16 CPU channels on the channel side and 24 peripheral devices on the port side. Further complexities arise by virtue of high data speeds employed between the CPU and a peripheral device making it desirable to take steps to avoid problems such as crosstalk, signal interference and poor conductor connections. It would be fair to state that once a large computer installation is connected and functioning properly, it is undesirable to physically remove a CPU or a peripheral device or even change connecting cables lest the physical disruption causes a malfunction that can disturb the entire system. System failures can be extremely costly, as much as thousands of dollars per minute.
Yet equipment malfunctions do occur and to a large extent the switch matrix interposed between the CPU and peripheral devices can be extremely effective in eliminating or bypassing such malfunctions. For example, in one exemplary prior art system as shown in FIG. 1, a multiple of CPUs 20.1, 20.2 are shown with their channels 24.1, 24.2 and 26.1, 26.2 connected to peripheral devices 28.1, 28.2 and 30.1, 30.2 through switch matrixes 32.1, 32.2. Each switch matrix has a display and control 34 with which a desired matrix configuration can be established and then so displayed.
Control over the matrix can be obtained with local switches at 36 or by way of a remote control system 38 connected to effect matrix configurations through interface units 40.1 and 40.2. The remote control employs a CRT 42 with a keyboard 44 and general purpose computer 46 is provided with suitable programs and a storage 48. These programs may provide alternate configurations that can be instantly applied to a switch matrix 32 so as to bypass a malfunctioning device or system. A large number of switch matrices 32 can be controlled with control 38 from a central console.
When a new peripheral device is to be connected to a CPU 20 care must still be taken to properly check out the compatability of the device with the CPU. In the parlance of the computer expert, this means testing the I/O (input and output) compatability of the CPU channel with the peripheral device. When the CPU is part of an IBM computer, the I/O between a channel and a peripheral device is a very complex series of signals and protocols. Such signals and protocols are described in the art and are generally known as evidenced by the large number of so-called IBM plug-compatible peripheral devices available from others than IBM. The I/O compatibility of pheripheral devices can be determined with a spare CPU, if one is available which is not often the case, or by using a CPU simulator. However, even when compatability is so determined, prudence dictates that a new peripheral device only be allowed to be connected to a system by a highly trained field engineer (the supervisory control suggested at 50) during prescribed system downtimes to assure that the device with its connecting cables will not disturb the installation. The examination of compatibility often then becomes time consuming, partly because the available time for this purpose is limited during any one month and the process itself appears to involve complex software analysis techniques.
In large computer installations where a large number of CPUs are used, it is common practice to provide an analysis of the loading or use made of the channels in a CPU. Thus, techniques exist with which the activities of the channels of any one CPU are compared and bar graphs representative of such use are displayed. Typically, the "Op-In" line of each channel of the CPUs is monitored. Although such activity monitoring indicates the use of the channels in any one CPU, the evenness of the loading between different CPUs is not compared. As a result, a user of such large computer installation prefers to connect his CPUs in a manner whereby some rough distribution of load is made. This is illustrated in FIG. 1 by the connection of all the "O" (24.1 and 26.1) channels of CPUs 20.1 and 20.2 to the same switch matrix 32.1 and similarly, all "F" channels (24.2 and 26.2) to switch matrix 32.2. Similar peripheral devices requiring generally the same amount of access to a CPU are then connected to the same switch matrix 32. Although this helps distribute the loading of the CPUs, the system operator still does not have adequate information on whether the configurations establish even or uneven loading to help in determining whether there is or is not a need to purchase additional equipment. Switch matrices have been provided with channel monitoring lights. However, their flickering does not really provide a reliable indication of channel usage.